Two types of non-volatile memory devices are floating gate type memory devices and floating trap type memory devices. A floating gate type memory device may include a control gate and a conductive floating gate that is isolated, by an insulating layer, from a substrate channel. Floating gate type memory devices may be programmed by storing charges as free carriers on the conductive floating gate.
Floating trap type memory devices may include a non-conductive charge storage layer between a gate electrode and a substrate. Floating trap type memory devices may be programmed by storing charges in traps in the non-conductive charge storage layer.
Floating gate type memory devices generally have a thicker tunneling insulating layer than floating trap type memory devices to provide comparable reliability for storing charges. A thicker tunneling insulating layer may result in an increased operating voltage for the memory device and an increased complexity of associated peripheral circuitry. Consequently, it may be more difficult to provide high integration density and low power consumption for floating gate type memory devices than for floating trap type memory devices.
A SONOS (silicon-oxide-nitride-oxide-semiconductor) structure of a conventional floating trap type unit memory device is shown in FIG. 1. The memory device includes a tunneling insulating layer 20, a charge storage layer 22, a blocking insulating layer 24, and a gate electrode 27 that are sequentially stacked on an active region of a P-type semiconductor substrate 10. An N+ type impurity diffusion layer 28 is formed at an active region on opposite sides of the gate electrode 27. The tunneling insulating layer 20 may include a thermal oxide material and the charge storage layer 22 may include silicon nitride material.
An energy band diagram of a floating trap type unit memory device is shown in FIG. 2, taken along a line I-I′ of FIG. 1. Intrinsic energy band gaps are shown for the materials corresponding to the semiconductor substrate 10, the tunneling insulating layer 20, the charge storage layer 22, the blocking insulating layer 24, and the gate electrode 27. Differences between the energy band gaps may result in potential barriers at the interfaces between the materials.
For example, the charge storage layer 22 can include silicon nitride which has an energy band gap of about 5 eV. The corresponding potential barriers between the tunneling insulating layer 20 and the charge storage layer 22 may be about 1 eV and 2 eV, respectively, for the conduction band and the valence band.
A silicon nitride layer is known to have three trap levels. A trap center of the silicon nitride layer includes a silicon atom that combines with three nitrogen atoms 20 and has one dangling bond. When no electron combines with the dangling bond (i.e., a hole combines therewith), the state may be called a first trap level E1. When one electron combines with the dangling bond, the state may be called a second trap level E2, which is higher than the first trap level E1. When two electrons combine with the dangling bond, the state may be called a third trap level E3, which is higher than the second trap level E2.
A floating trap type non-volatile memory device uses trap levels, such as those found in a silicon nitride layer, for memory operations. When a positive voltage is applied on the gate electrode 27, electrons are tunneled via the tunneling insulating layer 20 to become trapped in the charge storage layer 22. As the electrons are accumulated in the charge storage layer 22, a threshold voltage of the memory device is increased, and the memory device becomes programmed.
In contrast, when a negative voltage is applied to the gate electrode 27 as shown in FIG. 3, trapped electrons are discharged to the semiconductor substrate 10 via the tunneling insulating layer 20. Concurrently, holes become trapped in the first trap level E1 from the semiconductor substrate 10 by the tunneling insulating layer 20. Consequently, the threshold voltage of the unit memory device is decreased, and the memory device becomes erased.
For the memory device to be programmed, the quantity of charges from the channel should be relatively greater than the quantity of charges from the gate electrode. For example, when a positive voltage is applied to the gate electrode, if the quantity of holes provided from the gate electrode to the floating trap is equal to the quantity of electrons provided from the channel to the floating trap, negative charges are offset by positive charges and vice versa. Accordingly, the threshold voltage is not changed and programming may be precluded.
When the thickness of the silicon oxide layer, serving as a tunneling oxide layer, is 20 Å or less, current flow from direct tunneling may exceed current flow from F-N tunneling and an erase operation may occur. When a blocking oxide layer has a thickness of about 50 Å, charge may be primarily moved by F-N tunneling and the quantity of charges from the channel may be greater than the quantity of charges from the gate electrode. In contrast, when the thickness of the tunneling insulating layer is 20 Å or less and the blocking insulating layer is thicker than the tunneling insulating layer, charges may be primarily provided from the channel in erase and program operations, and the threshold voltage may be more easily controlled.
The thickness of the silicon oxide layer may affect the data retention time of the memory device. For example, when the thickness of the silicon oxide layer is 20 Å or less, charges stored in the floating trap may leak more easily and the data retention time of the memory device may be shortened. When the thickness of the silicon oxide layer is 20 Å or higher, the data retention time may be increased but the primary flow of charges to the floating trap may be by F-N tunneling. F-N tunneling may be more easily carried out as the effective mass of charge carriers becomes smaller and the electric field on the charge carrier path becomes stronger.
Conventional operations for programming and erasing a floating trap type memory device will now be described. During an early phase of a programming operation, when the tunneling insulating layer and the blocking insulating layer are oxide materials and a voltage is applied to the gate electrode, the generated electric field can be described by Equation 1 below.
                              E          ⁢                                          ⁢          ot                =                              E            ⁢                                                  ⁢            ob                    =                                    Vg              -                              Φ                ⁢                                                                  ⁢                m                ⁢                                                                  ⁢                s                            -                              2                ⁢                Φ                ⁢                                                                  ⁢                b                                                                    X                ⁢                                                                  ⁢                ot                            +                                                ɛ                  ⁡                                      (                    ot                    )                                                                    ɛ                  ⁡                                      (                    SIN                    )                                                              +                              X                ⁢                                                                  ⁢                ob                                                                        Equation        ⁢                                  ⁢        1            
The symbols “ot”, “ob”, and “SIN” represent the tunneling insulating layer, the blocking insulating layer, and the silicon nitride layer, respectively. The symbol “E” represents the electric field, “Vg” represents the voltage of a gate electrode, “Φms” represents a difference of a work function between the substrate and the gate electrode, “Φb” represents a substrate surface potential, “X” represents a thickness of the oxide layer, and “∈” represents a dielectric constant.
During the early phase of the programming operation, when a positive voltage is applied to the gate electrode, a hole is moved from the gate electrode to the floating trap and an electron is moved from the channel to the floating trap. When more electrons are provided to the gate electrode than holes, the threshold voltage is increased. As electrons become trapped in the floating trap of the charge storage layer and accumulate therein, the electric field applied to the blocking insulating layer may become stronger than the electric field applied to the tunneling insulating layer. Once stronger, trapped electrons become increasingly discharged via the blocking insulating layer, or holes become increasing injected from the gate electrode, so that growth of the threshold voltage becomes limited.
During an erasing operation, when a relatively lower voltage is applied to the gate electrode, electrons move by F-N tunneling from the gate electrode to the floating trap and holes move from the channel to the floating trap. Because the effective mass of electrons is lower than that of holes, electrons more easily flow from the gate electrode than holes from the channel. In an early phase of the erasing operation, when the floating trap of the silicon nitride layer (i.e., the charge storage layer) is uniformly filled with electrons, the quantity of charge, Q, may be negative. With a negative Q, the blocking insulating layer and the tunneling insulating layers can be described by Equations 2 and 3 below.
                              E          ⁢                                          ⁢          ot                =                              Vg            -                          Φ              ⁢                                                          ⁢              m              ⁢                                                          ⁢              s                        -                          Φ              ⁢                                                          ⁢              b                        -                          Q              ⁡                              (                                                                            X                      ⁢                                                                                          ⁢                      ot                                                              ɛ                      ⁡                                              (                        ob                        )                                                                              +                                                            X                      ⁢                                                                                          ⁢                      n                                                              2                      ⁢                                              ɛ                        ⁡                                                  (                          n                          )                                                                                                                    )                                                                        X              ⁢                                                          ⁢              ot                        +                          X              ⁢                                                          ⁢              n              ⁢                                                ɛ                  ⁡                                      (                    ot                    )                                                                    ɛ                  ⁡                                      (                    n                    )                                                                        +                          X              ⁢                                                          ⁢              ob                                                          Equation        ⁢                                  ⁢        2                                          E          ⁢                                          ⁢          ob                =                              E            ⁢                                                  ⁢            ot                    +                      Q                          ɛ              ⁡                              (                ot                )                                                                        Equation        ⁢                                  ⁢        3            
The symbols “ot”, “ob”, and “SIN” represent the tunneling insulating layer, the blocking insulating layer, and the silicon nitride layer, respectively. The symbol “E” represents an electric field, “Vg” represents a voltage of the gate electrode, “Φms” represents a difference of a work function between the substrate and the gate electrode, “Φb” represents a substrate surface potential, “X” represents a thickness of an oxide layer, and “Q” represents the quantity of charges at the silicon nitride layer.
When the thickness of the tunneling insulating layer is 20 Å or more, charges are moved at the tunneling insulating layer and the blocking insulating layer by F-N tunneling. During an erasing operation, the quantity of electrons provided from the gate electrode may exceed the quantity of holes provided from the channel and the floating trap can accumulate a negative charge, which may make it difficult to sufficiently decrease the threshold voltage to erase the memory.